SSPICR Interrupt Clear Register.
| RORIC | Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. |
| RTIC | Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |